1. Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, to an improvement in the arrangement of various circuits in semiconductor memory devices, such as, for example, a static random access memory (referred to hereinafter as a static RAM) or a dynamic random access memory (referred to hereinafter as a dynamic RAM).
2. Description of the Prior Art
FIG. 11 is a schematic block diagram showing the construction of a static RAM as an example of the conventional static semiconductor memory device. Such conventional static RAM is disclosed in, for example, Japanese Patent Laying-Open No. 63-893. Referring to FIG. 11, a memory cell array 1 is formed by a two-dimensional array of a plurality of memory cells, not shown, arranged in the column direction and in the row direction. A row address input signal supplied from outside of the static RAM is transmitted via a row address buffer 2 to a row decoder 3. The row decoder 3 is responsive to this row address input signal to select a row select line which is not shown (referred to hereinafter as a word line) for selecting memory cells constituting the memory cell array 1 row by row. Similarly, an externally supplied column address input signal is applied to a column decoder 5 via a column address buffer 4. The column decoder 5 is responsive to this column address input signal to drive a column select gate, not shown, as later described, to select each column of the memory cell array 1. During read-out, the data that is stored in the memory cell selected by the row decoder 3 and the column decoder 5 is read out via a read circuit 6 so as to be applied to a data output buffer 7. The read-out data is outputted via a terminal 8 from the data output buffer 7. On the other hand, during data writing, write data is entered via a terminal 9, and is applied via a data input buffer 10 to a write circuit 11. The write circuit 11 is responsive to the write data to write the data in the memory cell selected by the row decoder 3 and the column decoder 5. The operations of the read circuit 6, the data output buffer 7, the data input buffer 10 and the write circuit 11 are controlled by a read/write control circuit 13 responsive to a read/write control input signal supplied via a terminal 12.
FIG. 12 shows the construction of the memory cell array 1 of FIG. 11 in more detail. In the memory cell array 1 of FIG. 12, plural memory cell elements 14, each functioning as a data storage unit element, are arranged in a two-dimensional manner in the row direction and in the column direction. The memory cells 14 are connected to respective word lines 15 each for selecting the memory cells for one row. Each word line is selected by the row decoder 3.
The memory cells 14 of each column are connected to a pair of bit lines 16. It is by way of these bit line pairs that data are read out from the memory cells 14 or applied to the memory cells 14. Each bit line pair 16 has its one end connected to an associated clamping circuit 17, each clamping circuit 17 functioning as a bit line load for charging the associated bit line pair 16 to a predetermined potential. Each bit line pair 16 has its other end connected via an associated column select gate 18 to a read/write circuit 19. Each column select gate 18 is constituted by a pair of MOS transistors having their control electrodes connected in common. The control electrodes of these MOS transistors are supplied with a signal from a column decoder, not shown, such as the column decoder 5 of FIG. 11. As a result, one of a plurality of column select gates 18 is opened and one of a plurality of bit line pairs is selected and connected to the read/write circuit 19. This read/write circuit 19 has the function of both the read circuit 6 and the write circuit 11 shown in FIG. 11. This read/write circuit 19 is usually provided one for several columns of memory cells, such as, for example, a 2.sup.n number of columns (n being a positive integer). In this prior-art example, one read/write circuit 19 is provided for two consecutive columns.
The read/write operation of the memory cells shown in FIG. 12 is now explained. During read-out, the row decoder 13 is responsive to the row address input signal to select one of a large number of word lines 15 to which a memory cell from which data is desired to be read out is connected. This causes the data stored in the memory cells 14 connected to the selected word line 15 to appear on the associated bit line pairs 16.
The column decoder 5 is responsive to the column address input signal to turn on the MOS transistors of the column select gate 18 associated with the column including the memory cell from which the data is desired to be read out. As a result, the data stored in the memory cell 14 selected by the row decoder 3 and the column decoder 5 is transmitted via the bit line pair 16 and the column select gate 18 to the read/write circuit 19. The read-out circuit section, not shown, of the read/write circuit 19 is activated by the control signal from the read/write control circuit 13 of FIG. 11 to amplify signal data of extremely small amplitude read out from the memory cell 14 to output the amplified signal data to the outside via a data output buffer 7 shown in FIG. 11.
During writing, the write circuit section, not shown, of the read/write circuit 19 is activated by the control signal from the read/write control circuit 13 of FIG. 11 to write the data via a column select gate 18 and a bit line pair 16 in the desired memory cell selected in the same manner as during reading.
Meanwhile, the potentials at the non-selected bit line pairs are clamped by the above mentioned clamping circuits 17, each acting as a bit line load, at a suitable potential of not inverting the data of the memory cells.
The semiconductor memory device of the above described construction is disclosed in, for example, "a 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon" by T. Wada et al. appearing IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, pp. 727 to 732, issued in October, 1987.
In the above described conventional semiconductor memory device, a clamping circuit 17 and a column select gate 18 are required for each column or bit line pair 16. For keeping with the tendency towards a higher degree of integration, the width of each column is reduced, so that the widths of the clamping circuit 17 and the column select gate 18 need be reduced correspondingly. With the progress in the degree of integration, several problems have been presented in arranging the clamping circuits 17 and the column select gates 18 on the semiconductor chip. More specifically, in the memory cell array 1 shown in FIG. 12, the pitch of arrangement of the clamping circuit 17 and the column select gate 18 on the semiconductor chip is dominated by the one having a larger width of the clamping circuit 17 and the column select gate 18. That is, in the memory cell array 1 of FIG. 12, since the clamping circuit 17 has a larger width than the column select gate 18, the pitch of arrangement is dominated only by the width of the clamping circuit 17, such that a certain limit is placed on improving circuit integration thus resulting in the limited degree of freedom in circuit designing.
In addition, in the above described conventional semiconductor memory device, read/write circuits are arranged at a rate of one for several columns, for example, two columns in the prior-art example of FIG. 12. Thus, when the bit line pair width is reduced to keep pace with the high integration, the following problem is presented in arranging the read/write circuits on the semiconductor chip. That is, in FIG. 12, the transverse length, or width, of the read/write circuit corresponds to two bit line pairs. Since each memory cell is made up of four transistors, only several transistors can be arrayed over an extent limited by such width. However, inasmuch as the read/write circuit 19 is usually made up of several tens of transistors, the longitudinal extent of the read/write circuit 19 is necessarily increased with the result that the arrangement of the read/write circuits becomes difficult on the semiconductor chip so that the degree of freedom in circuit designing is correspondingly limited.
On the other hand, the Japanese Patent Laying-Open No. 63-10396 discloses an intersecting system of bit lines in the semiconductor memory device. However, there is not shown as yet a construction in which the bit line pairs are bent or turned down substantially in the two-dimensional form of a letter U.